cirrus logic er578e2 www.cirrus.com/ may ?04 1 copyright ? cirrus logic, inc. 2004 (all rights reserved) 5/13/2004 errata: CS8416 rev. d rev. d silicon (reference CS8416 datasheet revision ds578pp4) ? parts with a manufacturing date code of 0415 or after will not output a proper clock on rmck when the rmck output frequency is set to be 128*fs. parts with a manufacturing date code befor e 0415 will output a proper clock on rmck when the rmck output frequency is set to be 128*fs. all parts will output a proper clock on rmck when the rmck output frequency is set to be 256*fs. this problem will be corrected and operate properly in rev e. ? when omck system clock mode is enabl ed (swclk=1b) and the differential xlr or single ended rca cable has been plugged and unplugged from the receiver input multiple times, the clock output on the rmck pin may not properly switch over from the recovered master clock to the omck clock when the receiver pll is unlocked. olrck and osclk are always divided from the clock output on the rmck pin. if the receiver inputs are always le ft connected, only unplugged during power down, or connected using an optical connector, omck system clock mode will function correctly. if the application requires the receiver inputs to be rapidly plugged and unplugged multiple times and omck system clock mode is required, there is a software mode workaround. the user can monitor the unlock bit in the receiver error register (0ch) either by po lling or by using the interrupt function. when unlock=1b, the user should set the fswclk bit in the control0 register (00h) to 1b. when unlock=0b, the user should set the fswclk bit in the control0 register (00h) to 0b. there is no workaround for hardware mode. this problem will be corrected and operate properly in rev e. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find one nearest you go to www.cirrus.com
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